Interlayer engineering for enhanced ferroelectric tunnel junction operations in HfO x-based metal-ferroelectric-insulator-semiconductor stack

Abstract

Ferroelectric tunnel junction (FTJ) has been considered as a promising candidate for next-generation memory devices due to its non-destructive and low power operations. In this article, we demonstrate the interlayer (IL) engineering in the FTJs to boost device performances. Through the analysis on the material and electrical characteristics of the fabricated FTJs with engineered IL stacks, it is clearly found that the insertion of an Al2O3 layer between the SiO2 insulator and the pure-HfO (x) FE improves the read disturbance (2V (c) = 2.2 V increased), the endurance characteristics (tenfold improvement), and the cell-to-cell TER variation simultaneously without the degradation of the ferroelectricity (less than 5%) and the polarization switching speeds through grain size modulation. Based on these investigations, the guidelines of IL engineering for low power ferroelectric devices were provided to obtain stable and fast memory operations.