Thermally Activated Defect Engineering for Highly Stable and Uniform ALD-Amorphous IGZO TFTs with High-Temperature Compatibility
- Authors
- Kim, Dong-Gyu; Lee, Won-Bum; Lee, Seunghee; Koh, Jihyun; Kuh, Bongjin; Park, Jin-Seong
- Issue Date
- Jul-2023
- Publisher
- AMER CHEMICAL SOC
- Keywords
- atomic layer deposition (ALD); IGZO; thin-filmtransistor (TFT); Al2O3; gateinsulator; deposition temperature; positive biastemperature stress (PBTS)
- Citation
- ACS APPLIED MATERIALS & INTERFACES, v.15, no.30, pp.36550 - 36563
- Indexed
- SCIE
SCOPUS
- Journal Title
- ACS APPLIED MATERIALS & INTERFACES
- Volume
- 15
- Number
- 30
- Start Page
- 36550
- End Page
- 36563
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/189427
- DOI
- 10.1021/acsami.3c06517
- ISSN
- 1944-8244
- Abstract
- Highly stable IGZO thin-film transistors derived fromatomic layerdeposition are crucial for the semiconductor industry. However, unavoidabledefect generation during high-temperature annealing results in abnormalpositive bias temperature stress (PBTS). Herein, we propose a defectengineering method by controlling the gate insulator (GI) depositiontemperature. Applying a GI deposition temperature of 400 & DEG;C tothe In0.52Ga0.18Zn0.30O active layereffectively suppresses defects even after 600 & DEG;C annealing, preservingthe amorphous phase of IGZO. The device exhibits a threshold voltage(V (TH)) of 0.05 V, a field-effect mobilityof 27.6 cm(2)/Vs, a subthreshold swing of 61 mV/decade, anda hysteresis voltage of 0.01 V, demonstrating highly reliable PBTSand negative bias temperature stress. A power-law fit of the PBTSstability under 2 MV/cm of gate field stress and 120 & DEG;C of temperaturestress predicts a V (TH) shift of -0.01V after 10 years. Moreover, the proposed method ensures reliable uniformityover a large 4 in. area.
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