Double-gate tunnel field-effect transistor with inner doping and spacer regions
- Authors
- Kim, Hyun Woo; Kwon, Daewoong
- Issue Date
- Dec-2020
- Publisher
- IOP PUBLISHING LTD
- Keywords
- Tunnel FET; subthreshold swing; band-to-band tunneling
- Citation
- JAPANESE JOURNAL OF APPLIED PHYSICS, v.59, no.12, pp.126505-1 - 126505-7
- Indexed
- SCIE
SCOPUS
- Journal Title
- JAPANESE JOURNAL OF APPLIED PHYSICS
- Volume
- 59
- Number
- 12
- Start Page
- 126505-1
- End Page
- 126505-7
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/190131
- DOI
- 10.35848/1347-4065/abc926
- ISSN
- 0021-4922
- Abstract
- In this study, a tunnel field-effect transistor (FET) with source-side inner doping and a drain-side spacer is proposed to obtain high current drivability and reduced gate-to-drain capacitance, simultaneously. The effects of the inner doping region (region(inner)) are investigated with various lengths (L-ID) and concentrations (N-ID). As the N-ID increases, the more source-to-region(inner) tunneling is added to conventional source-to-channel tunneling and thus the total tunneling current is enhanced. Moreover, with a wider L-ID, the on-current is reduced by the wider source-to-region(inner) tunneling width and the source-to-region(inner) tunneling is generated at a lower gate voltage by the L-ID-induced limitation of energy band bending. Also, the impact of the inner spacer is evaluated with various inner spacer lengths (L-IS). By introducing the inner spacer, the gate-to-drain capacitance can be significantly reduced. Consequently, the proposed tunnel FET has a reduced gate-to-drain capacitance as well as an increased tunneling current, which leads an improvement in switching delay.
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