Demonstration of Tunneling Field-Effect Transistor Ternary Inverter
- Authors
- Kim, Hyun Woo; Kim, Sihyun; Lee, Kitae; Lee, Junil; Park, Byung-Gook; Kwon, Daewoong
- Issue Date
- Oct-2020
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Ternary inverter; TFET ternary CMOS (T-CMOS); tunnel FETs (TFET); vertical TFET
- Citation
- IEEE TRANSACTIONS ON ELECTRON DEVICES, v.67, no.10, pp.4541 - 4544
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON ELECTRON DEVICES
- Volume
- 67
- Number
- 10
- Start Page
- 4541
- End Page
- 4544
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/190133
- DOI
- 10.1109/TED.2020.3017186
- ISSN
- 0018-9383
- Abstract
- We demonstrate tunnel FET (TFET)-based ternaryCMOS (T-CMOS) which can operate at supply voltage (V-DD) < 0.6 V. The TFET T-CMOS consists of the vertical n/p TFETs and their drain current (I-D)-gate voltage (V-G) characteristics have sub-60mV/dec steep subthreshold swing (SS) and hump as the gate and source are overlapped. To verify the formation mechanism of the third output voltage state (V-3rd) in the TFET T-CMOS, I-D-V(G)s are analyzed with respect to various drain voltages (V-D). As a result, it is revealed that I-D-V(G)s of the n/p TFETs can have the wider flat ON-current regions at smaller VD by drain-side channel inversion and stable V-3rd can be formed through the voltage dividing between them. Furthermore, it is found that the hump plays a role to make the steeper output voltage transitions by increasing the I-D difference between the n/p TFETs.
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