Volatile and Nonvolatile Characteristics of Asymmetric Dual-Gate Thyristor RAM with Vertical Structure
- Authors
- Kim, Hyun-Min; Kwon, Dae Woong; Kim, Sihyun; Lee, Kitae; Lee, Junil; Park, Euyhwan; Lee, Ryoongbin; Kim, Hyungjin; Kim, Sangwan; Park, Byung-Gook
- Issue Date
- Sep-2018
- Publisher
- AMER SCIENTIFIC PUBLISHERS
- Keywords
- 1T-DRAM; Capacitor-Less DRAM; Thyristor; Dual-Gate
- Citation
- JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, v.18, no.9, pp.5882 - 5886
- Indexed
- SCIE
- Journal Title
- JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY
- Volume
- 18
- Number
- 9
- Start Page
- 5882
- End Page
- 5886
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/190943
- DOI
- 10.1166/jnn.2018.15570
- ISSN
- 1533-4880
- Abstract
- In this paper, the volatile and nonvolatile characteristics of asymmetric dual-gate thyristor random access memory (TRAM) are investigated using the technology of a computer-aided design (TCAD) simulation. Owing to the use of two independent gates having different gate dielectric layers, volatile and nonvolatile memory functions can be realized in a single device. The first gate with a silicon oxide layer controls the one-transistor dynamic random access memory (1T-DRAM) characteristics of the device. From the simulation results, a rapid write speed (<8 ns) and a large on-off current ratio (> 10(7) ) can be achieved. The second gate, whose dielectric material is composed of oxide/nitride/oxide (O/N/O) layers, is used to implement the nonvolatile property by trapping charges in the nitride layer. In addition, this offers an advantage when processing the 3D-stack memory application, as the device has a vertical channel structure with polycrystalline silicon.
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