Response speed of negative capacitance FinFETs
- Authors
- Kwon, Daewoong; Liao, Yu-Hung; Lin, Yen-Kai; Duarte, Juan Pablo; Chatterjee, Korok; Tan, Ava J.; Yadav, Ajay K.; Hu, Chenming; Krivokapic, Zoran; Salahuddin, Sayeef
- Issue Date
- Jun-2018
- Publisher
- Institute of Electrical and Electronics Engineers
- Citation
- DIGEST OF TECHNICAL PAPERS - SYMPOSIUM ON VLSI TECHNOLOGY, v.2018-June, pp.49 - 50
- Indexed
- SCOPUS
- Journal Title
- DIGEST OF TECHNICAL PAPERS - SYMPOSIUM ON VLSI TECHNOLOGY
- Volume
- 2018-June
- Start Page
- 49
- End Page
- 50
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/191517
- DOI
- 10.1109/VLSIT.2018.8510626
- ISSN
- 0743-1562
- Abstract
- We report on the measurement of a 101-stage ring oscillator (RO) consisting of state-of-the-art 14 nm FinFET devices with a ferroelectric gate layer that exhibits negative capacitance. We show that the gate stage delay as a function of applied voltage can be directly modeled from DC characteristics of the individual NC-nFET and NC-pFET devices that constitute the RO, thereby demonstrating that there is no slowdown of the NC effect at the highest speed tested-per-stage delay as small as 7.2 ps.
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