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An Analysis of Current-mode Drivers in 40-nm CMOS Technology
- Authors
- Lim, Bona; Jo, Hanhee; Han, Jaeduk
- Issue Date
- Oct-2023
- Publisher
- IEEE
- Keywords
- cascode current-mode logic (CML); design tradeoffs; high-speed link transmitters; tailless CML
- Citation
- Proceedings - International SoC Design Conference 2023, ISOCC 2023, pp 355 - 356
- Pages
- 2
- Indexed
- SCOPUS
- Journal Title
- Proceedings - International SoC Design Conference 2023, ISOCC 2023
- Start Page
- 355
- End Page
- 356
- ISSN
- 2163-9612
2472-9655
- Abstract
- This paper compares two prominent high-speed link transmitter driver topologies, cascode current-mode logic (CML) and tailless CML, exploring their design tradeoffs. Analysis and simulation results reveal that the cascode CML exhibits higher output resistance due to the presence of a tail current source, while the tailless CML demonstrates faster operation with reduced output capacitance. Additionally, this study highlights the tradeoff between driver output swing and power consumption.
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Related Researcher
- Han, Jaeduk
- COLLEGE OF ENGINEERING (SCHOOL OF ELECTRONIC ENGINEERING)