Exploring FeFET Degradation Mechanisms: Mid-Interlayer as a Viable Solution for Stable Retention, Disturb Immunity, and Low Vth Variation

Abstract

This study experimentally investigates the unexplored dynamics of retention loss, disturbance, and V<inf>th</inf> instability in MIFIS FeFETs, featuring a metal-gate interlayer (G.IL)-ferroelectric (FE)-channel interlayer (Ch.IL)-Si stack. To prevent undesired decoupling of polarization (P) and trapped charges during performance degradation, a mid-interlayer (mid-IL) within the FE layer is proposed. The optimized mid-IL (i) stabilizes the FE phase in the HfZrO<inf>x</inf> (HZO) film, (ii) acts as an energy barrier in the gate stack to suppress trapped charge loss toward the channel, and (iii) mitigates channel percolation issues caused by the polymorphic and polycrystalline nature of FE films. These improvements enable an advanced gate stack design with reduced operation voltage (V<inf>PGM</inf>/V<inf>ERS</inf>:17/ - 14 V), a wide memory window (MW: 10.5 V), stable TLC retention (F Δ MW∼-6% after 10 years at 85°C), disturb immunity (Δ V<inf>th</inf>=0 after 104 cycles at 12 V), and low V<inf>th</inf> variation (54% Δ V<inf>ih</inf> reduction).