A 0.5–1-V Time–Voltage Hybrid Domain Dual-Loop Analog LDO With Wide-Bandwidth High PSR in 28 nm

Abstract

This article presents a time and voltage hybrid domain (HD) nested dual-loop analog low-dropout (LDO) regulator that achieves both wide-frequency-range high power supply rejection (PSR) and fast transient response at sub-1 V. Time-domain (TD) regulation is employed to provide a high dc gain even at a low-supply voltage, enabling fine regulation and low-frequency-range high PSR. A voltage-domain (VD) regulation method comprising an analog error amplifier (AMP) only provides low gain at a low-supply voltage; however, due to its continuous operation, the VD regulation method can improve both the load transient response and high-frequency PSR, which are the limitations of the clock (CLK)-synchronized TD regulation method including the authors’ prior work. The proposed LDO has a nested dual-loop structure, enabling it to fully exploit the advantages of two domains: the TD-regulated outer loop and the VD-regulated inner loop, for wide-bandwidth high PSR and fast transient response. The proposed LDO fabricated in the 28-nm process operates in the 0.5–1-V supply voltage range and achieves high PSRs of up to <inline-formula> <tex-math notation=LaTeX>$-$</tex-math> </inline-formula>73 and <inline-formula> <tex-math notation=LaTeX>$-$</tex-math> </inline-formula>22 dB at 10 kHz and 10 MHz, respectively. In addition, the regulator shows a 158-mV undershoot and fast settling time of 23.3 ns with a load current step that changes from 0.1 to 100 mA in 10 ns, achieving a figure-of-merit (FOM) of 11.28 ps.