Enhancing Program Speed and Diminishing Read After Write Delay by Metal Work Function Engineering

Abstract

We investigate the impact of gate metal work function (ФM) engineering on the performance of Metal - Interlayer – Ferroelectric (FE) – Interlayer – Silicon (MIFIS) ferroelectric field effect transistors (FeFET). The gate injected trapped charge (Qit’) plays a critical role in determining key device parameters such as the memory window (MW) and operating voltage (Vop), making ФM optimization a viable approach to enhance MIFIS FeFET performance. To evaluate this effect, we fabricated devices with Al (ФM = 4.1 eV), TiN (ФM = 4.7 eV), Pt (ФM = 5.35 eV) gate metals. A higher ФM reduces the valence band offset at the gate interlayer (G.IL), facilitating hole injection during program (PGM) operations. This results in a lower PGM Vop and a steeper incremental step pulse programming (ISPP) profile. Simulation results confirm that enhanced gate hole injection underpins the observed ISPP behavior. Additionally, high ФM gates reduce read after write delay (RAWD) and lower de-trap pulse amplitudes. Our findings establish gate ФM engineering as an effective strategy to improve MIFIS FeFET performance, particularly for low-voltage operation and disturbance mitigation.