Detailed Information

Cited 0 time in webofscience Cited 0 time in scopus
Metadata Downloads

An Inductive Loading Simultaneous Noise and Input Matching Technique with Current Reuse for Low-Power LNA

Authors
Huynh, Phuoc B. T.Lee, Gyeong-SeokPark, Jun-YoungYun, Tae-Yeoul
Issue Date
Jul-2025
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Keywords
Logic gates; Impedance; Noise; Loading; Resistance; Noise measurement; Inductors; Impedance matching; Capacitance; Transconductance; Capacitive loading simultaneous noise and input matching (CLSNIM); inductive loading SNIM (ILSNIM); power constrained SNIM (PCSNIM); simultaneous noise and input matching (SNIM)
Citation
IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.60, no.7, pp 2461 - 2472
Pages
12
Indexed
SCIE
SCOPUS
Journal Title
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume
60
Number
7
Start Page
2461
End Page
2472
URI
https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/210455
DOI
10.1109/JSSC.2024.3511578
ISSN
0018-9200
1558-173X
Abstract
This article presents an inductive loading simultaneous noise and input matching (ILSNIM) technique for a low-power low-noise amplifier (LNA). In contrast to conventional simultaneous noise and input matching (SNIM) methods, where lossy resistance associated with an on-chip low-Q gate inductor substantially degrades the total noise figure (NF) performance, the input stage of the proposed LNA exploits the gate-drain capacitance feedback incorporated with inductive loading for the first time to construct the input impedance network. This design approach overcomes the NF limitation in conventional SNIM techniques by eliminating the lossy gate inductor while boosting the transconductance to achieve SNIM under low power consumption. Furthermore, a current-reuse structure with a cascaded stage is applied not only to enhance the overall gain but also to generate a noiseless resistive component that addresses the instability issue without adverse impacts on other performances. Fabricated using a 0.11- μm complementary metal-oxide-semiconductor (CMOS) process, the proposed ILSNIM LNA demonstrates a gain of 13.6 dB, an NF of 2.8 dB, and a third-order input intercept point (IIP3) of - 5.2 dBm at 6.8 GHz under a 1.2-mW power dissipation from a 1-V supply.
Files in This Item
Go to Link
Appears in
Collections
서울 공과대학 > 서울 융합전자공학부 > 1. Journal Articles

qrcode

Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.

Related Researcher

Researcher Yun, Tae Yeoul photo

Yun, Tae Yeoul
COLLEGE OF ENGINEERING (SCHOOL OF ELECTRONIC ENGINEERING)
Read more

Altmetrics

Total Views & Downloads

BROWSE