Positive Interaction between Charge Trapping and Polarization Switching in Metal-Interlayer-Ferroelectric-Interlayer-Silicon (MIFIS) Ferroelectric Field-Effect Transistor

Abstract

This study employs analytical simulation to illustrate the beneficial correlation between interface trapped charge and spontaneous polarization (P-S) switching behavior in the MIFIS gate stack. We found that there is a positive interaction between charge trapping and polarization switching, comprising three sequential processes. 1) In the process of program (erase) operation, electrons (holes) are introduced from the gate metal and are trapped at the interface between the gate interlayer (gate-IL) and the ferroelectric layer. 2) The trapped charge amplifies the electric field across the ferroelectric (FE) layer, subsequently enhancing P-S. 3) The increase in P-S intensified the induced field on the gate-IL which boosts the charge injection. The three processes are reiterated as previously mentioned. The results indicate that the significant memory window (MW) observed in MIFIS ferroelectric field-effect transistor (FeFET) is a consequence of the combined effect of trapped charges and polarization switching charges, rather than separate contributions. Lastly, with the calibrated simulation model, we provide strategies to improve the device performance in terms of MW and operation speed. The experimental findings and analytic comprehension in this work provide a foundation for future researches on FeFET.