A Highly Reliable Ferroelectric NAND Cell with Ultra-thin IGZO Charge Trap Layer: Trap Profile Engineering for Endurance and Retention Improvement

Abstract

We demonstrate a ferroelectric NAND (FeNAND) cell featuring an engineered InGaZnO (IGZO) charge trap layer (CTL) for reliable 3D integration. To overcome endurance degradation and severe memory window (MW) loss during retention in conventional metal-gate interlayer (G.IL)-ferroelectric (FE)-channel interlayer (Ch.IL)-Si (MIFIS) gate stacks, we propose a metal-G.IL-oxide semiconductor (OS)-FE-Ch.IL-Si (MISFIS) structure incorporating a 2 nm-thick IGZO CTL. The IGZO CTL simultaneously serves as an oxygen reservoir to suppress oxygen vacancy (VO) formation in the FE layer and provides an energy band offset to reduce charge loss. In-situ N2 doping is applied to tailor the trap profile, achieving deep-level dominant traps at a 2 sccm flow rate. This optimized design enables a wide MW of 9.4 V with a low operation voltage (VOP) below 17 V, stable triple-level cell (TLC) retention over 10 years, and robust endurance exceeding 80k program/erase (PGM/ERS) cycles. These results validate the MISFIS FeNAND as a promising architecture for next-generation 3D FE memories.