Imprinted Antiferroelectric with Low Damage Process for High Performance Negative Capacitance NAND Flash Memory

Abstract

The concept of negative capacitance (NC), originating from the intrinsic energy configuration of HZO ferroelectrics, has been predominantly utilized in logic transistors to achieve a steeper Id-Vg characteristic. Departing from these conventional approaches, we have developed an NC-NAND flash memory by integrating the NC phenomenon into the blocking oxide layer of conventional NAND flash memory. By leveraging the capacitance boosting effect of the NC-integrated blocking oxide (BO) layer, we can significantly enhance program (PGM) efficiency and lower the operating voltage of charge trap memory. In this work, we propose two combined approaches to improve the NC. First, we applied asymmetric tensile stress to the HZO layer through high-pressure annealing (HPA), thereby generating an internal electric field across the HZO layer. Additionally, we improved the polarization property of the HZO layer by employing a low-damage process during the deposition of the capping TiN electrode, minimizing interfacial damage to the HZO surface. Step-pulsed I-V measurement confirmed that the capacitance boosting effect of the NC blocking oxide with the low-damage process was improved by 16.7%, while the operating voltage was reduced by 1 V. Additionally, the NC-NAND flash memory with the low-damage process exhibited a significant higher ISPP slope characteristic.