Ultrathin-Mo-Enabled NC-NAND with Sub-3.5nm HZO for Scalable High-MW Operation

Abstract

We present a device-level integration strategy for implementing negative-capacitance (NC) in charge trap flash (CTF) memory to achieve low programming voltage (VPGM) and enhanced reliability. Robust ferroelectricity and active NC behavior are realized in sub-3.5 nm HfZrO2 (HZO) by engineering an ultrathin Mo bottom electrode, effectively minimizing hole critical dimension (CD) scaling penalties. To ensure thermal stability during 3D integration, an oxide semiconductor channel is employed. Erase (ERS) performance is further improved via a source-tied covering metal (SCM) that reinforces voltage distribution during ERS operations. In addition, interfacial band engineering using a TiO2 layer at the blocking oxide (BO)/charge trap layer (CTL) interface suppresses unwanted electron injection, improving endurance and multi-level reliability. The resulting NC-NAND cell exhibits a wide memory window (~13 V), supporting stable triple-level cell (TLC) operation. These results demonstrate the scalability and energy efficiency of NC-NAND for next-generation 3D flash memory.