Decoupling and Quantifying Polarization and Trap Charges in MIFIS FeNAND: Insights into Charge Dynamics and Reliability

Abstract

We propose a novel measurement methodology to decouple and quantify spontaneous polarization (ΔPS), channel-injected trap charge (ΔQit), and gate-injected trap charge ( Δ Qit′ ) in the metal-insulator-ferroelectric-insulator-semiconductor (MIFIS) FeNAND devices. By analyzing devices with varying gate interlayer (G.IL) thicknesses (30, 35, and 40 Å), we extracted charge dynamics with delay time (td), separating contributions from charge components (ΔPS, ΔQit, and ΔQit′). Using time- and gate bias-dependent measurements, distinct memory window (MW) behaviors were identified: read-after-write delay (RAWD) dominates MW degradation in the program (PGM) state, while charge loss governs the erase (ERS) state. Additionally, we confirmed that the FE and channel interlayer (Ch.IL) act as the primary tunneling paths despite the presence of the gate interlayer (G.IL). Finally, endurance cycling analysis reveals a significant reduction in ΔPS, while ΔQit and Δ Qit′ remain stable, indicating an increasing role of trap charges in MW control with cycling. This framework enables the design of FeNAND with improved reliability characteristics.