Band Engineering of Gate Interlayer for Low-voltage Operation and Enhanced Reliability in Gate-injection Type FeFETs

Abstract

A Metal-Gate Insulator (Gate IL)–Charge Trap Layer (CTL)–Ferroelectric (FE)–Channel Insulator (Channel IL)–Si (MINFIS) structure is proposed. The incorporation of the CTL enhances charge storage and broadens the memory window (MW), but it also results in a higher operating voltage compared with the conventional MIFIS structure. To address this limitation, we introduce an OTO (SiO2/TiO2/SiO2) Gate IL to replace the conventional ONO (SiO2/Si3N4/SiO2), and comparatively analyze the two structures. The OTO Gate IL reduces the operating voltage by incorporating a high-k TiO2 layer, which increases the electric field across the ferroelectric under the same applied bias and thereby accelerates the positive feedback between charge injection and ferroelectric switching. As a result, the OTO-MINFIS FeFET maintains a wide MW of 10.8 V while lowering the operating voltage to +18.5/–15.5 V, corresponding to a maximum reduction of 20.5% relative to the ONO-MINFIS device, when evaluated at the full achievable MW. Endurance tests up to 5 × 103 program/erase (PGM/ERS) cycles performed at an identical MW (~5 V) show ~5× smaller MW degradation. Post-cycling retention, measured up to 104 s, exhibits 32% lower ΔMW, confirming the superior reliability of the OTO stack. These findings demonstrate that Gate IL engineering with an OTO stack is an effective approach for achieving low-voltage and reliable ferroelectric memory devices.