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Atomic Layer Deposition Process-Enabled Carrier Mobility Boosting in Field-Effect Transistors through a Nanoscale ZnO/IGO Heterojunction

Authors
Seul, Hyeon JooKim, Min JaeYang, Hyun JiCho, Min HoeCho, Min HeeSong, Woo-BinJeong, Jae Kyeong
Issue Date
Jul-2020
Publisher
AMER CHEMICAL SOC
Keywords
heterojunction; atomic layer deposition; indium gallium oxide; zinc oxide; field-effect transistor; bias stability
Citation
ACS APPLIED MATERIALS & INTERFACES, v.12, no.30, pp.33887 - 33898
Indexed
SCIE
SCOPUS
Journal Title
ACS APPLIED MATERIALS & INTERFACES
Volume
12
Number
30
Start Page
33887
End Page
33898
URI
https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/9695
DOI
10.1021/acsami.0c06382
ISSN
1944-8244
Abstract
Low-temperature (<= 400 degrees C), stackable oxide semiconductors are promising as an upper transistor ingredient for monolithic three-dimensional integration. The atomic layer deposition (ALD) route provides a low-defect, high-quality semiconducting oxide channel layer and enables accurate controllability of the chemical composition and physical thickness as well as excellent step coverage on nanoscale trench structures. Here, we report a high-mobility heterojunction transistor in a ternary indium gallium zinc oxide system using the ALD technique. The heterojunction channel structure consists of a 10 nm thick indium gallium oxide (IGO) layer as an effective transporting layer and a 3 nm thick, wide band gap ZnO layer. The formation of a two-dimensional electron gas was suggested by controlling the band gap of the IGO quantum well through In/Ga ratio tailoring and reducing the physical thickness of the ZnO film. A field-effect transistor (FET) with a ZnO/In0.83Ga0.17O1.5 heterojunction channel exhibited the highest field-effect mobility of 63.2 +/- 0.26 cm(2)/V s, a low subthreshold gate swing of 0.26 +/- 0.03 V/dec, a threshold voltage of -0.84 +/- 0.85 V, and an I-ON/OFF ratio of 9 x 10(8). This surpasses the performance (carrier mobility of similar to 41.7 +/- 1.43 cm(2)/V s) of an FET with a single In0.83Ga0.17O1.5 channel. Furthermore, the gate bias stressing test results indicate that FETs with a ZnO/In1-xGaxO1.5 (x = 0.25 and 0.17) heterojunction channel are much more stable than those with a single In1-xGaxO1.5 (x = 0.35, 0.25, and 0.17) channel. Relevant discussion is given in detail on the basis of chemical characterization and technological computer-aided design simulation.
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