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A 30 Gb/s All-Digital CDR with a phase error compensator
- Authors
- Park, Kunhoo; K.; Hwang, Heejae; H.; Kim, Jongsun; J.
- Issue Date
- 2020
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Keywords
- CDR; Clock and Data Recovery; SerDes
- Citation
- 2020 International Conference on Electronics, Information, and Communication, ICEIC 2020
- Journal Title
- 2020 International Conference on Electronics, Information, and Communication, ICEIC 2020
- ISSN
- 0000-0000
- Abstract
- A 30 Gb/s all-digital clock and data recovery (CDR) circuit with a new phase error compensator is presented. The proposed phase error compensator removes the jitter component of the recovered clock that is unnecessarily increased by the error information generated by the samplers in the over-sampling CDRs. The proposed 30 Gb/s all-digital CDR is implemented in a 65-nm CMOS process and achieves a peak-to-peak recovered clock jitter of 5.09 ps. The proposed CDR dissipates 75 mW (=2.5 mW/Gbps) from a 1.2 supply. © 2020 IEEE.
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Related Researcher
- Kim, Jong Sun
- Engineering (Electronic & Electrical Engineering)