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Programmable fractional-ratio frequency multiplying clock generator
- Authors
- Han, Sangwoo; Kim, Jintae; Kim, Jongsun
- Issue Date
- 30-Jan-2014
- Publisher
- INST ENGINEERING TECHNOLOGY-IET
- Keywords
- amplifiers; analogue-digital conversion; charge-coupled device circuits; integrated circuit noise; signal conditioning circuits; word length 9 bit; gain 0 dB to 18 dB; VGA; variable-gain amplifier; CCD signal amplitude; noise elimination; correlated double sampling circuit; CCD signal processing; charge coupled device signal processing; CDS circuit
- Citation
- ELECTRONICS LETTERS, v.50, no.3, pp.163 - +
- Journal Title
- ELECTRONICS LETTERS
- Volume
- 50
- Number
- 3
- Start Page
- 163
- End Page
- +
- ISSN
- 0013-5194
- Abstract
- A new programmable delay-locked loop ( DLL) based fractional frequency multiplying clock generator is presented. In contrast to conventional DLL-based clock generators that generate only integer clock multiplication, the proposed clock generator provides fractional-ratio frequency multiplication while maintaining the advantages of DLLs, such as the deskewing between the input and the output clocks. Implemented in a 0.13 mu m 1.2 V CMOS process, the proposed clock generator achieves an effective peak-to-peak jitter of 7.5 ps and occupies an active area of 0.018 mm(2) while dissipating 9.0 mW at 1.5 GHz. The output frequency ranges from 0.85 to 1.5 GHz with programmable fractional multiplication ratios of N/M, where N=4, 5, 8, 10 and M=1, 2, 3.
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Related Researcher
- Kim, Jong Sun
- Engineering (Electronic & Electrical Engineering)