A high-resolution wide-range dual-loop digital delay-locked loop using a hybrid search algorithm
- Authors
- Han, S.; Kim, J.
- Issue Date
- 2012
- Citation
- Proceedings - 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC, pp.293 - 296
- Journal Title
- Proceedings - 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC
- Start Page
- 293
- End Page
- 296
- URI
- https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/19111
- DOI
- 10.1109/IPEC.2012.6522683
- ISSN
- 0000-0000
- Abstract
- This paper presents a dual-loop digital delay-locked loop (DLL) for high-speed DRAM applications. The dual-loop architecture using a hybrid (binary + sequential) search algorithm is proposed to achieve both wide-range operation and high delay resolution while maintaining the closed-loop property that allows for tracking of PVT variations. A new phaseinterpolation range selector (PIRS) and a variable successive approximation register (VSAR) algorithm are adopted to resolve the boundary switching and harmonic locking problems of conventional digital DLLs. The proposed digital DLL, implemented in a 0.18-μm CMOS process, occupies an active area of only 0.19mm2 and operates over a wide frequency range of 0.15-1.5 GHz. The DLL also dissipates a power of 11.3 mW from a 1.8 V supply at 1 GHz. The measured peak-to-peak output clock jitter is 24 ps with an input clock jitter of 7.5 ps at 1.5 GHz. The delay resolution is only 2.2 ps. © 2012 IEEE.
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