Electrical characteristics of the three-dimensional interconnection structure for the chip stack package with Cu through vias
- Authors
- Lee, Kwang-Yong; Oh, Teck-Su; lee, Jae-Ho; Oh, Tae-Sung
- Issue Date
- Feb-2007
- Publisher
- SPRINGER
- Keywords
- chip stack package; system in package; Cu via; electroplating; interconnection
- Citation
- JOURNAL OF ELECTRONIC MATERIALS, v.36, no.2, pp.123 - 128
- Journal Title
- JOURNAL OF ELECTRONIC MATERIALS
- Volume
- 36
- Number
- 2
- Start Page
- 123
- End Page
- 128
- URI
- https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/23641
- DOI
- 10.1007/s11664-006-0020-5
- ISSN
- 0361-5235
- Abstract
- A chip stack specimen of a three-dimensional (3-D) interconnection structure with Cu vias of 75-mu m diameter, 90-mu m height, and 150-mu m pitch was successfully fabricated using via hole formation with deep reactive ion etching (RIE), Cu via filling with pulse-reverse pulse electroplating, Si thinning, Cull Sn bump formation, and flip-chip bonding. The contact resistance of a Cu/Sn bump joint and Cu via resistance could be determined from the slope of the daisy chain resistance versus the number of bump joints of the flip-chip specimen containing Cu vias. When the flip chip was bonded at 270 degrees C for 2 min, the contact resistance of a Cu/Sn bump joint of 100-mu m diameter was 6.74 m Omega, and the resistance of a Cu via of 75-mu m diameter and 90-mu m height was 2.31 m Omega. As the power transmission characteristics of the Cu through via, the S-21 parameter was measured up to 20 GHz.
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Collections - College of Engineering > Materials Science and Engineering Major > 1. Journal Articles
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