A 7.68 GHz Fast-Lock Low-Jitter Digital MDLL
- Authors
- Jin, J.; Kim, S.; Choi, S.; Lee, P.-H.; Rhee, S.-J.; Choi, K.-H.; Kim, J.
- Issue Date
- 2021
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Keywords
- Clock Generator; Frequency Multiplication; MDLL
- Citation
- Proceedings - International SoC Design Conference 2021, ISOCC 2021, pp.311 - 312
- Journal Title
- Proceedings - International SoC Design Conference 2021, ISOCC 2021
- Start Page
- 311
- End Page
- 312
- URI
- https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/27835
- DOI
- 10.1109/ISOCC53507.2021.9613940
- ISSN
- 0000-0000
- Abstract
- A 7.68 GHz fast-lock digital multiplying delay-locked loop (MDLL) is presented. Implemented in a 40-nm 1.2-V CMOS process, the proposed MDLL achieves an output frequency of 7.68 GH with a high frequency multiplication factor N = 64. By adopting a cyclic Vernier TDC, the proposed MDLL achieves a fast lock time of 6 reference cycles. To reduce jitter integration caused by power supply noise, a differential pair based digitally controlled oscillator (DCO) is adopted. Also, to reduce deterministic jitter, a DSM-based dithering jitter reduction scheme has been adopted. The proposed MDLL achieves a simulated p-p jitter of about 16 ps at 7.68 GHz. It occupies an active area of 0.026 mm2, and dissipates 29 mW at 7.68 GHz. © 2021 IEEE.
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Collections - College of Engineering > School of Electronic & Electrical Engineering > 1. Journal Articles
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