A 0.1-1.5 GHz All-Digital Phase Inversion Delay-Locked Loop
- Authors
- Han, Sangwoo; Kim, Taejin; Kim, Jongsun
- Issue Date
- 2013
- Publisher
- IEEE
- Citation
- PROCEEDINGS OF THE 2013 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), pp.341 - 344
- Journal Title
- PROCEEDINGS OF THE 2013 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC)
- Start Page
- 341
- End Page
- 344
- URI
- https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/29604
- Abstract
- An all-digital, wide-range phase inversion delay-locked loop (PIDLL) with a high-resolution duty-cycle corrector (DCC) is presented. The proposed PIDLL utilizes a new phase inversion scheme to reduce the total number of delay elements (DEs) in the digitally controlled delay line (DCDL) by approximately one-half, enabling shorter locking times, lower power consumption, reduced jitter performance, and a smaller area, while maintaining a wide operating frequency range. To achieve high delay resolution and linear delay characteristics, a three-stage DCDL using a new area-efficient digital feedback delay element (FDE) is proposed. The FDE is also utilized to implement a new DCC that obtains a duty-cycle error of less than +/- 0.85% over a 30-70% input duty-cycle range. The proposed DCC-equipped PIDLL is implemented in a 0.13-mu m CMOS process, occupies an area of 0.11 mm(2), and operates over a wide frequency range of 0.1-1.5 GHz. It dissipates power of 5.9 mW from a 1.2 V supply at 1 GHz and exhibits a peak-to-peak output clock jitter of 11.25 ps at 1.5 GHz.
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Collections - College of Engineering > School of Electronic & Electrical Engineering > 1. Journal Articles
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