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A High-Performance, Low-Power 8-Bit Full-Adder Using 8+T Differential SRAM for Computation-inMemory
- Issue Date
- 1-Jan-2022
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Keywords
- Full-Adder; In-Memory Computing(IMC); Process-in-Memory(PIM); SRAM; XOR operator
- Citation
- Proceedings - International SoC Design Conference 2022, ISOCC 2022, pp.131 - 132
- Journal Title
- Proceedings - International SoC Design Conference 2022, ISOCC 2022
- Start Page
- 131
- End Page
- 132
- ISSN
- 0000-0000
- Abstract
- As the amount of data increases in the era of artificial intelligence (AI), in-memory computing (IMC) circuits are being studied to solve the von Neumann bottleneck, a problem in modern computer architecture. This paper proposes an XOR operator based on 8+T differential static random-access memory (8+T SRAM) and an 8-bit Full-Adder based on it. Simulation results in 65 nm show that the XOR operation is 47% faster than the previous method, the Full-Adder is 43% faster, consumes 32% less energy with 14% less transistor. © 2022 IEEE.
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Related Researcher
- Kim, Young min
- Engineering (Electronic & Electrical Engineering)