A fast-locking harmonic-free digital DLL for DDR3 and DDR4 SDRAMs
- Authors
- Yoon, Junsub; Heo, Seo Weon; Kim, Jongsun
- Issue Date
- 25-Jan-2017
- Publisher
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
- Keywords
- delay-locked loop; DDR3; DDR4; SDRAM; harmonic-free; DLL
- Citation
- IEICE ELECTRONICS EXPRESS, v.14, no.2
- Journal Title
- IEICE ELECTRONICS EXPRESS
- Volume
- 14
- Number
- 2
- URI
- https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/6170
- DOI
- 10.1587/elex.13.20161020
- ISSN
- 1349-2543
- Abstract
- A new digital delay-locked loop (DLL) for DDR3/DDR4 SDRAM is presented. The proposed digital DLL employs a new noisetolerant triple (MSB-interval + binary + sequential) search algorithm for implementing a harmonic-free, fast-locking capability while retaining low jitter, low power performance, and a wide operating frequency range. The proposed DLL with duty-cycle correction is designed using a 38-nm CMOS process and occupies an active area of just 0.02mm(2). The DLL operates over a frequency range of 0.3-2.0 GHz and achieves a peak-to-peak jitter of 7.78 ps and dissipates 3.48mW from a 1.1V supply at 1 GHz.
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