An Area-Efficient Multi-Phase Fractional-Ratio Clock Frequency Multiplier
- Authors
- Han, Sangwoo; Lim, Jongtae; Kim, Jongsun
- Issue Date
- Feb-2016
- Publisher
- IEEK PUBLICATION CENTER
- Keywords
- DLL; multiplying DLL; MDLL; frequency multiplier; clock multiplier; multi-phase clock
- Citation
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.16, no.1, pp.143 - 146
- Journal Title
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
- Volume
- 16
- Number
- 1
- Start Page
- 143
- End Page
- 146
- URI
- https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/8166
- DOI
- 10.5573/JSTS.2016.16.1.143
- ISSN
- 1598-1657
- Abstract
- A new area-efficient multi-phase clock frequency multiplier is presented. The proposed fractional-ratio frequency multiplying DLL (FFMDLL) is implemented in a 65 nm CMOS process and occupies an active area of just 0.01 mm(2). The proposed FFMDLL provides 8-phase output clocks and achieves a frequency range of 0.6-1.0 GHz with programmable multiplication ratios of N/M, where N = 4, 5, 8, 10 and M = 1, 2, 3. It achieves an effective peak-to-peak jitter of 5 ps and dissipates 3.4 mW from a 1.0 V supply at 1 GHz.
- Files in This Item
- There are no files associated with this item.
- Appears in
Collections - College of Engineering > School of Electronic & Electrical Engineering > 1. Journal Articles
![qrcode](https://api.qrserver.com/v1/create-qr-code/?size=55x55&data=https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/8166)
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.