EMC Qualification Methodology for Semicustom Digital Integrated Circuit Design

Abstract

In this paper, a simulation methodology and an electromagnetic compatibility qualification environment (EQE) are developed to verify the electromagnetic susceptibility of semicustom digital integrated circuits (IC) during the design phase. The immunity levels of the digital circuits are estimated by the functional failure and delay change caused by the external noise which is injected by bulk current injection (BCI) and direct power injection (DPI) methods. The model for the device under test (DUT), the standard cell parasitic model, and the equivalent circuit model of BCI and DPI test setup are developed for the IC immunity test. All test components and on-chip circuit models are linked by EQE to analyze the target DUT. The EQE can be applied to predict the immunity level of the design at the schematic level and postlayout level design. To validate the accuracy of the proposed simulation tool, EQE is applied to the design process of a clock divider (CKD) and a serial peripheral interface (SPI) circuits to verify their immunity levels. The CKD and SPI circuits are designed and fabricated using Magna 180 nm Complementary metal-oxide semiconductor (CMOS) technology. The immunity levels generated by the EQE are compared with the experimental measurement results. The comparison shows good agreement between simulation and measurement.