A digitally controlled phase-locked loop with a digital phase-frequency detector for fast acquisition
- Authors
- Hwang, I.-C.; Song, S.-H.; Kim, S.-W.
- Issue Date
- Oct-2001
- Publisher
- IEEE
- Citation
- IEEE Journal of Solid-State Circuits, v.36, no.10, pp 1574 - 1581
- Pages
- 8
- Journal Title
- IEEE Journal of Solid-State Circuits
- Volume
- 36
- Number
- 10
- Start Page
- 1574
- End Page
- 1581
- URI
- https://scholarworks.bwise.kr/cau/handle/2019.sw.cau/26313
- DOI
- 10.1109/4.953487
- ISSN
- 0018-9200
- Abstract
- A digitally controlled phase-locked loop (DCPLL) that achieves fast acquisition by employing a digital phase-frequency detector (DPFD) and a variable loop gain scheme was developed for an advanced clock synthesizer and was fabricated in a 3.3-V 0.6-μm CMOS process. The DPFD was developed to measure the frequency difference and to generate digital outputs corresponding to the difference. Using these features, the DCPLL achieves ideally one-cycle frequency acquisition when programmed with an appropriate gain. The experimental results show that the fabricated DCPLL exhibits three-cycle and one-cycle frequency acquisitions, when locking to 400 MHz (VCO at 800 MHz) and 200 MHz (VCO at 400 MHz), respectively.
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Collections - College of ICT Engineering > School of Electrical and Electronics Engineering > 1. Journal Articles
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