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낮은 Subthreshold 누설전류를 갖는 CMOS 논리회로CMOS Logic Circuits with Lower Subthreshold Leakage Current
- Authors
- 송상헌
- Issue Date
- Oct-2004
- Publisher
- 대한전기학회
- Keywords
- CMOS; Subthreshold; Leakage Current; Logic Circuit; Inverter
- Citation
- 전기학회논문지 C권, v.53, no.10-C, pp 500 - 504
- Pages
- 5
- Journal Title
- 전기학회논문지 C권
- Volume
- 53
- Number
- 10-C
- Start Page
- 500
- End Page
- 504
- ISSN
- 1229-246X
- Abstract
- We propose a new method to reduce the subthreshold leakage current. By moving the operating point of OFF state MOSFETs through input-controlled voltage generators, logic circuits with much lower leakage current can be built with few extra components. SPICE simulation results for the new inverter show correct logic results without speed degradation compared to a conventional inverter.
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