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A novel high performance junctionless FETs with saddle-gate
- Authors
- Jin, Xiaoshi; Wu, Meile; Liu, Xi; Chuai, Rongyan; Kwon, Hyuck-In; Lee, Jung-Hee; Lee, Jong-Ho
- Issue Date
- Sep-2015
- Publisher
- SPRINGER
- Keywords
- Saddle-gate; Junctionless; Field effect transistors; Design optimization
- Citation
- JOURNAL OF COMPUTATIONAL ELECTRONICS, v.14, no.3, pp 661 - 668
- Pages
- 8
- Journal Title
- JOURNAL OF COMPUTATIONAL ELECTRONICS
- Volume
- 14
- Number
- 3
- Start Page
- 661
- End Page
- 668
- ISSN
- 1569-8025
- Abstract
- In this paper, a novel junctionless field effect transistors (JL FETs) with a saddle-gate structure has been proposed, and the I-V characteristics has been extensively studied by TCAD device simulation. The performance comparison between saddle-gate JL FETs and conventional triple-gate JL FETs has also been performed. The influence of gate dielectric on device property has also been investigated. A scheme of design optimization of saddle-gate JL FETs has also been proposed.
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