Source optimization for DRAM critical layer with minimum optical proximity correction

Abstract

With the introduction of Extreme Ultraviolet (EUV) lithography, DRAM chips now have the potential to be patterned at the 10 nm node. DRAM critical layers, which include the Bit-Line Periphery (BLP) and Storage Node Landing Pad (SNLP), are strong candidates for EUV patterning. To print diverse patterns on a layer, various approaches, such as double exposure, have been explored to achieve successful patterning. Moreover, Optical Proximity Correction (OPC) is essential to accurately print the designed patterns onto the wafer. However, as the feature size of the target design decreases, the corresponding reduction in mask pattern dimensions leads to increased complexity in OPC computation due to Mask Rule Check (MRC) constraints. In this study, we discuss a source optimization method to minimize OPC challenges and enable single-exposure patterning for DRAM critical layers. By applying an optimized illumination system, we demonstrate the ability to print patterns with high fidelity while simultaneously achieving high imaging performance and sufficient process margin.