Sublayer dependent thermal deformation during EUV exposure

Abstract

The theoretical resolution limit of high-NA EUV lithography remains uncertain, particularly regarding its feasibility for direct printing of P16 line/space. The vertically stacked interconnect layers are increasingly integrated to enhance device performance beyond resolution constraints. However, this approach introduces thermomechanical challenges. This work investigates the impact of thermal stress on EUV lithography in advanced three-dimensional wafer structures, which are crucial for future nodes. Finite element simulations reveal that increasing layer counts exacerbate thermomechanical mismatch, leading to greater in-plane deformation during EUV exposure. Simulations based on representative logic and DRAM structures show that as material diversity increases, thermal deformation rises. Additionally, an increase in exposure dose further amplifies deformation differences across sublayer stacks, potentially degrading overlay accuracy between EUV layers. These findings highlight the growing complexity of overlay control in multi-layered EUV processes.