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Time-multiplexed test access architecture for stacked integrated circuitsopen access
- Issue Date
- Jul-2016
- Publisher
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
- Keywords
- 3D test access architecture; design-for-testability; stacked-ICs
- Citation
- IEICE ELECTRONICS EXPRESS, v.13, no.14, pp.1 - 6
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEICE ELECTRONICS EXPRESS
- Volume
- 13
- Number
- 14
- Start Page
- 1
- End Page
- 6
- ISSN
- 1349-2543
- Abstract
- Due to ever-increasing gap between (1) the tester-channel and scan-shift frequencies, and (2) the wafer-level and package-level test frequencies, the tester-channel frequency is underutilized for stacked-ICs. Thus, we present a novel time-multiplexed test access architecture for SICs that complies with P1838 and it significant reduces test time, which reduction is observed on a synthetic SIC based on ITC'02 benchmark SoCs.
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