Effect of Parasitic Resistance and Capacitance on Performance of InGaAs HEMT Digital Logic Circuits

Abstract

In this brief, the impact of parasitic resistance and capacitance on InGaAs HEMT digital logic circuits is investigated via device simulations and circuit analysis. We present the correlation between device geometry and circuit delay for various structural scenarios. When the gate-to-S/D contact distance L-sg is scaled down to logic device standards, high integration density and additional circuit performance can be expected as compared with experimental devices that are demonstrated to date. This brief highlights the importance of engineering the device structure outside the channel region to achieve high device performance and device density. Scaled InGaAs HEMTs show superior performance over experimental devices and 27% less power consumption for the same circuit-speed constraint.