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Physics-Based Compact Model of III-V Heterostructure FETs for Digital Logic Applications
- Authors
- Oh, Saeroonter; Wong, H. -S. Philip
- Issue Date
- Dec-2008
- Publisher
- IEEE
- Citation
- IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2008, TECHNICAL DIGEST, pp.1 - 4
- Indexed
- SCIE
SCOPUS
- Start Page
- 1
- End Page
- 4
- ISSN
- 0163-1918
- Abstract
- A physics-based analytical compact model of InGaAs FETs for logic applications is developed. This model neither heavily depends on parameter extraction nor requires any time-consuming computation, enabling digital circuit design and circuit-level performance estimation for III-V FETs. The model captures SCE, trapezoidal well QW energies and capacitances including 2D potential profile information.
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Related Researcher
- OH, SAE ROON TER
- ERICA 공학대학 (SCHOOL OF ELECTRICAL ENGINEERING)