고속/고밀도 VLSI 회로의 공진현상을 감소시키기 위한 효율적인 파워/그라운드 네트워크 설계Effective Power/Ground Network Design Techniques to suppress Resonance Effects in High-Speed/High-Density VLSI Circuits
- Other Titles
- Effective Power/Ground Network Design Techniques to suppress Resonance Effects in High-Speed/High-Density VLSI Circuits
- Authors
- 류순걸; 어영선; 심종
- Issue Date
- Jul-2006
- Publisher
- 대한전자공학회
- Keywords
- resonance; ground bounce; on-chip decoupling capacitor; signal integrity
- Citation
- 전자공학회논문지, v.43, no.7, pp 29 - 37
- Pages
- 9
- Indexed
- KCI
- Journal Title
- 전자공학회논문지
- Volume
- 43
- Number
- 7
- Start Page
- 29
- End Page
- 37
- URI
- https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/44764
- ISSN
- 1229-6368
- Abstract
- 본 논문에서는 온칩 디커플링 커패시터에 의한 파워/그라운드 라인에서의 RLC 공진현상을 감소시키기 위한 해석적인 모델을 제시한다. 패키지 인덕턴스와 온칩 디커플링 커패시터 및 출력 드라이버로 인하여 형성되는 RLC 공진 회로의 공진주파수를 정확하게 예측하였다. 예측된 공진주파수를 이용하여 회로 동작에 필요한 적절한 디커플링 커패시터의 크기를 결정할 수 있다. 본 논문에서 제시한 공진현상을 감소시킬 수 있는 새로운 설계 방법의 타당성은 0.18㎛ 공정 HSPICE 모델을 사용한 시뮬레이션을 통하여 검증하였다.
This paper presents a new analytical model to suppress RLC resonance effects which inevitably occur in power/ground lines due to on-chip decoupling capacitor and other interconnect circuit parasitics (i.e., package inductance, on-chip decoupling capacitor, and output drivers, etc.). To characterize the resonance effects, the resonance frequency of the circuit is accurately estimated in an analytical manner. Thereby, a decoupling capacitor size to suppress the resonance for a suitable circuit operation is accurately determined by using the estimated resonance frequency. The developed novel design methodology is verified by using 0.18㎛ process-based-HSPICE simulation.
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