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Efficient signal integrity verification method of multi-coupled RLC interconnect lines with asynchronous circuit switching
- Authors
- Je, Taeyong; Eo, Yungseon
- Issue Date
- Mar-2006
- Publisher
- IEEE
- Citation
- Proceedings - International Symposium on Quality Electronic Design, ISQED, pp 419 - 424
- Pages
- 6
- Indexed
- OTHER
- Journal Title
- Proceedings - International Symposium on Quality Electronic Design, ISQED
- Start Page
- 419
- End Page
- 424
- ISSN
- 1948-3287
1948-3295
- Abstract
- A new signal integrity verification method of integrated circuit interconnects with asynchronous circuit switching is presented. A ramp input is modeled with delayed step inputs. Then signal transient variations due to asynchronous input signal switching are accurately as well as efficiently determined by using traveling-wave-based waveform approximation (TWA) technique. It is shown that using 90nm technology, the signal timing and crosstalk of multi-coupled lines with asynchronous switching inputs have an excellent agreement with SPICE simulation but its computation time is several thousand times faster than that of SPICE simulation using generic segment-based RLC circuit model. © 2006 IEEE.
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Related Researcher
- EO, YUNG SEON
- ERICA 공학대학 (SCHOOL OF ELECTRICAL ENGINEERING)