ScholarWorks@Hanyang University

Browsing by Jang, Jun-HwanAuthor

All A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
전체 가 나 다 라 마 바 사 아 자 차 카 타 파 하

Showing results 1 to 4 of 4

SCIESCOPUS
A 0.5-1 V,-68 dB Power Supply Rejection Capacitorless Analog LDO Using Voltage-to-Time Conversion in 28-nm CMOSGo to Link

Jang, Jun-Hwan; Gwon, Hui-Dong; Kong, Tae-Hwang; Yang, Jun-Hyeok; Choi, Byong-Deok

ArticleIssue Date2022CitationIEEE JOURNAL OF SOLID-STATE CIRCUITS, v.57, no.8, pp 2462 - 2473PublisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
SCIESCOPUS
A 0.5–1-V Time–Voltage Hybrid Domain Dual-Loop Analog LDO With Wide-Bandwidth High PSR in 28 nmGo to Link

Jang, Jun-Hwan; Gwon, Hui-Dong; Yoo, Sungmin; Yang, Jun-Hyeok; Choi, Byong-Deok

ArticleIssue Date2025CitationIEEE Journal of Solid-State Circuits, v.60, no.1, pp 272 - 285PublisherInstitute of Electrical and Electronics Engineers
SCISCIESCOPUS
A High-Reliability Carry-Free Gate Driver for Flexible Displays Using a-IGZO TFTsGo to Link

Kim, Jong-Seok; Byun, Jung-Woo; Jang, Jun-Hwan; Kim, Yong-Duck; Han, Ki-Lim; Park, Jin-Seong; Choi, Byong-Deok

ArticleIssue Date2018CitationIEEE Transactions on Electron Devices, v.65, no.8, pp 3269 - 3276PublisherInstitute of Electrical and Electronics Engineers
SCISCIESCOPUS
Dynamic Logic Circuits Using a-IGZO TFTsGo to Link

Kim, Jong Seok; Jang, Jun-Hwan; Kim, Yong-Duck; Byun, Jung-Woo; Han, Kilim; Park, Jin-Seong; Choi, Byong-Deok

ArticleIssue Date2017CitationIEEE Transactions on Electron Devices, v.64, no.10, pp 4123 - 4130PublisherInstitute of Electrical and Electronics Engineers
1
CONTACT US

RSS_1.0 RSS_2.0 ATOM_1.0

222, Wangsimni-ro, Seongdong-gu, Seoul, 04763, Korea+82-2-2220-1366

COPYRIGHT © 2024 HANYANG UNIVERSITY.

Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.
You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.

BROWSE

한국어