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Anomalously Beneficial Gate-Length Scaling Trend of Negative Capacitance Transistors

Authors
Liao, Yu-HungKwon, DaewoongLin, Yen-KaiTan, Ava JiangHu, ChenmingSalahuddin, Sayeef
Issue Date
Nov-2019
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Keywords
Logic gates; Capacitance; Iron; Market research; MOSFET; Ferroelectric materials; Negative capacitance; ferroelectric; short channel effects
Citation
IEEE ELECTRON DEVICE LETTERS, v.40, no.11, pp.1860 - 1863
Indexed
SCIE
SCOPUS
Journal Title
IEEE ELECTRON DEVICE LETTERS
Volume
40
Number
11
Start Page
1860
End Page
1863
URI
https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/189909
DOI
10.1109/LED.2019.2940715
ISSN
0741-3106
Abstract
The Negative Capacitance Field Effect Transistors exhibit excellent SS and DIBL improvements from the control MOSFET devices at very short gate lengths, a phenomenon which cannot be explained using conventional MOSFET theory. This benefit arises from an effect which acts similarly to decreasing the equivalent-oxide thickness at short gate lengths. The effect is observed in both TCAD simulations and experiments, and is explained by the conjunction of the source/drain inner fringing field and the nonlinear polarizability of ferroelectric materials. The results present a sharp contrast to conventional scaling theory and bode well for extending the MOSFET gate length scaling limit.
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COLLEGE OF ENGINEERING (SCHOOL OF ELECTRONIC ENGINEERING)
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