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Challenges to Partial Switching of Hf0.8Zr0.2O2 Gated Ferroelectric FET for Multilevel/Analog or Low-voltage Memory Operation
- Authors
- Chatterjee, Korok; Kim, Sangwan; Karbasian, Golnaz; Kwon, Daewoong; Tan, Ava J.; Yadav, Ajay K.; Serrao, Claudy R.; Hu, Chenming; Salahuddin, Sayeef
- Issue Date
- Sep-2019
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Ferroelectric; hafnium zirconium oxide; memory; gate last; silicon-on-insulator; neuromorphic computing; deep learning; artificial intelligence
- Citation
- IEEE ELECTRON DEVICE LETTERS, v.40, no.9, pp.1423 - 1426
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE ELECTRON DEVICE LETTERS
- Volume
- 40
- Number
- 9
- Start Page
- 1423
- End Page
- 1426
- ISSN
- 0741-3106
- Abstract
- The ability to partially switch an FeFET could enable their use as an embedded low-voltage memory and as analog weight storage in artificial neural networks (ANNs). We report on memory characterization of FeFETs gated with 5.5-nm Hf0.8Zr0.2O2, fabricated on fully depleted silicon-on-insulator using a self-aligned, gate last process. We find that for a single device, excellent elevated temperature retention, program/erase endurance, and read endurance are obtained; however, there is significant device to device variability in the response of the ferroelectric to a partially switching program pulse, which may require the use of feedback in programming.
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Related Researcher
- Kwon, Daewoong
- COLLEGE OF ENGINEERING (SCHOOL OF ELECTRONIC ENGINEERING)