Design Methodology for Low-Voltage Operational (≤1 V) FRAM Cell Capacitors and Approaches for Overcoming Disturb Issues in 1T-nC Arrays: Experimental & Modeling

Abstract

In this work, we provide a methodology for designing an anti-ferroelectric (AFE) based FRAM cell capacitor that operates at low voltage (≤ 1 V), while achieving superior high and steep polarization (∆P) switching characteristics (23.5 μC/cm2), considering BEOL compatibility (process temp. ≤ 400 ℃). Furthermore, through experimental demonstration and modeling, we validate that the steep ∆P switching, closely related to the domain size of the AFE material, is a key enabler for mitigating disturbance issues in 1T-nC FRAM arrays. Our reliable model framework, calibrated with physical and structural parameters, determines the optimal number of stacks for the 3D 1T-nC FRAM architecture from the perspective of disturbance characteristics. This work highlights the potential of hafnia-based materials in embedded cache memory, bridging the gap between Δ P functionality and reliability.