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In-situ Surface Energy Engineering for ALD-Derived Highly Reliable Top Gate In2O3 Thin-Film Transistors
- Authors
- Eun Oh, Jeong; Hee Choi, Cheol; Kim, Taikyu; Hun Yoon, Seong; Woong Bang, Seon; Chae, Jiwon; Im, Changik; Hee Cho, Min; Yun, Pilsang; Ha, Daewon; Kyeong Jeong, Jae
- Issue Date
- Nov-2025
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Atomic layer deposition; bias temperature stability; indium oxideindium oxide; surface energy; surface energy; thin-film transistor; thin-film transistor; thin-film transistor
- Citation
- IEEE ELECTRON DEVICE LETTERS, v.46, no.11, pp 2050 - 2053
- Pages
- 4
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE ELECTRON DEVICE LETTERS
- Volume
- 46
- Number
- 11
- Start Page
- 2050
- End Page
- 2053
- ISSN
- 0741-3106
1558-0563
- Abstract
- This study investigates the effects of in-situ surface energy engineering applied prior to the deposition of the top gate dielectric on the electrical performance of In<inf>2</inf>O<inf>3</inf> TFTs. O<inf>2</inf> plasma treatment effectively reduces the interfacial trap density at the In<inf>2</inf>O<inf>3</inf>/gate dielectric interface, enhancing the overall device performance. Notably, In<inf>2</inf>O<inf>3</inf> TFTs subjected to an optimized oxygen plasma treatment duration of 3 sec exhibited significant improvements in electrical characteristics, including a high field-effect mobility of 84.3 cm2/V·s, a steep subthreshold swing of 76.8 mV/dec, and a minimal threshold voltage shift of 20 mV under rigorous bias temperature stress conditions (an electric field of 4 MV/cm at 85 °C for 3600 sec).
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Related Researcher
- Jeong, Jae Kyeong
- COLLEGE OF ENGINEERING (SCHOOL OF ELECTRONIC ENGINEERING)