Design Techniques for a 60 Gb/s 173 mW Wireline Receiver Frontend in 65 nm CMOS Technology
- Authors
- Han, Jae duk; Lu, Yue; Sutardja, Nicholas; Jung, Kwangmo; Alon, Elad
- Issue Date
- Apr-2016
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Chip-to-chip communication; current integration; decision feedback equalizer (DFE); feedforward equalizer (FFE); high-speed links
- Citation
- IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.51, no.4, pp.871 - 880
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE JOURNAL OF SOLID-STATE CIRCUITS
- Volume
- 51
- Number
- 4
- Start Page
- 871
- End Page
- 880
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/23184
- DOI
- 10.1109/JSSC.2016.2519389
- ISSN
- 0018-9200
- Abstract
- Design techniques for a complete 60 Gb/s receiver frontend with equalization, output slicing/demultiplexing, and clocking capabilities are described. Current integration combined with a cascode gate-voltage bias gain-control technique enables energy-efficient implementation of CTLE, FFE, and DFE circuits while operating near the speed limits of the technology. Despite following the DFE that has already in principle sliced the data, adaptive error-sampling requires high gain to resolve small residual error signals-this challenge is addressed by the addition of interleaved, offset-canceled deserializing samplers. Clock generation as well as distribution circuits are implemented to complete the receiver frontend. The proposed 65 nm CMOS receiver operates at 60 Gb/s, consuming 173 mW from 1.2 V and 1.0 V supplies.
- Files in This Item
-
Go to Link
- Appears in
Collections - 서울 공과대학 > 서울 융합전자공학부 > 1. Journal Articles
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.