Design Techniques for a 60-Gb/s 288-mW NRZ Transceiver With Adaptive Equalization and Baud-Rate Clock and Data Recovery in 65-nm CMOS Technology
- Authors
- Han, Jae duk; Sutardja, Nicholas; Lu, Yue; Alon, Elad
- Issue Date
- Dec-2017
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Chip-to-chip communication; clock and data recovery (CDR); current integration; decision feedback equalizer (DFE); feed-forward equalizer (FFE); high-speed links
- Citation
- IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.52, no.12, pp.3474 - 3485
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE JOURNAL OF SOLID-STATE CIRCUITS
- Volume
- 52
- Number
- 12
- Start Page
- 3474
- End Page
- 3485
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/3950
- DOI
- 10.1109/JSSC.2017.2740268
- ISSN
- 0018-9200
- Abstract
- Design techniques for a complete 60-Gb/s non-return-to-zero transceiver with adaptive equalization as well as baud-rate clock and data recovery (CDR) are demonstrated. A complete equalization front end with per-path adaptation and per-sampler offset calibration enables 60-Gb/s operation over realistic channels. Current integration in the front end for energy-efficient equalization is combined with integration phase dithering to realize a robust baud-rate CDR. Correlation of the adaptive error sampler output with the phase dithering sequence indicates the direction of phase offset, and the resulting baud-rate CDR saves power and complexity compared to an oversampling CDR by not requiring additional clock phases/deserializers. The proposed 65-nm CMOS transceiver operates at 60 Gb/s with an eye opening of 30% UI and consumes 288 mW while equalizing 21 dB of loss at 30 GHz over a 0.7-m Twinax cable.
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