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SCIESCOPUS
A Physics-Based Compact Model of III-V FETs for Digital Logic Applications: Current-Voltage and Capacitance-Voltage CharacteristicsGo to Link

Oh, Saeroonter; Wong, H. -S. Philip

ArticleIssue Date2009CitationIEEE TRANSACTIONS ON ELECTRON DEVICES, v.56, no.12, pp.2917 - 2924PublisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
SCISCIESCOPUS
Artificial optic-neural synapse for colored and color-mixed pattern recognitionGo to Linkopen access

Seo, Seunghwan; Jo, Seo-Hyeon; Kim, Sungho; Shim, Jaewoo; Oh Seyong; Kim, Jeong-Hoon; Heo, Keun; Choi, Jae-Woong; Choi, Changhwan; Oh, Saeroonter, et al.

ArticleIssue Date2018CitationNature Communications, v.9, no.1, pp 1 - 8PublisherNature Publishing Group
SCIESCOPUS
Effect of Parasitic Resistance and Capacitance on Performance of InGaAs HEMT Digital Logic CircuitsGo to Link

Oh, Saeroonter; Wong, H. -S. Philip

ArticleIssue Date2009CitationIEEE TRANSACTIONS ON ELECTRON DEVICES, v.56, no.5, pp.1161 - 1164PublisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
SCIE
Hole mobility characteristics under electrical stress for surface-channel germanium transistors with high-k gate stackGo to Link

Yi, Jeong-Hyong; Oh, Saeroonter; Wong, H. -S. Philip

ArticleIssue Date2008CitationJAPANESE JOURNAL OF APPLIED PHYSICS, v.47, no.4, pp.2544 - 2547PublisherJAPAN SOCIETY APPLIED PHYSICS
SCIESCOPUS
Impact of III-V and Ge Devices on Circuit PerformanceGo to Link

Park, Jeongha; Oh, Saeroonter; Kim, SoYoung; Wong, H. -S. Philip; Wong, S. Simon

ArticleIssue Date2013CitationIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.21, no.7, pp.1189 - 1200PublisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
SCIESCOPUS
Physics-Based Compact Model for III-V Digital Logic FETs Including Gate Tunneling Leakage and Parasitic CapacitanceGo to Link

Oh, Saeroonter; Wong, H. -S. Philip

ArticleIssue Date2011CitationIEEE TRANSACTIONS ON ELECTRON DEVICES, v.58, no.4, pp.1068 - 1075PublisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
SCIESCOPUS
Technology Assessment Methodology for Complementary Logic Applications Based on Energy-Delay OptimizationGo to Link

Wei, Lan; Oh, Saeroonter; Wong, H. -S. Philip

ArticleIssue Date2011CitationIEEE TRANSACTIONS ON ELECTRON DEVICES, v.58, no.8, pp.2430 - 2439PublisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
SCIESCOPUS
Viability Study of All-III-V SRAM for Beyond-22-nm Logic CircuitsGo to Link

Oh, Saeroonter; Wong, H. -S. Philip

ArticleIssue Date2011CitationIEEE ELECTRON DEVICE LETTERS, v.32, no.7, pp.877 - 879PublisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
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