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Fault Current Limiter and Mechanical DC CB based Protection against Valve-side SPG Faults in HB-MMC Bipolar Systemopen access

Authors
Usman, MuhammadKwak, Yu-JinLee, Bang-Wook
Issue Date
Apr-2025
Publisher
Institute of Electrical and Electronics Engineers Inc.
Keywords
DC circuit breaker; MMC-HVDC bipolar links; Passive oscillation DC circuit breaker; PSCAD/EMTDC program; single-phase valve-side MMC fault
Citation
IEEE Access, v.13, pp 59826 - 59840
Pages
15
Indexed
SCIE
SCOPUS
Journal Title
IEEE Access
Volume
13
Start Page
59826
End Page
59840
URI
https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/125283
DOI
10.1109/ACCESS.2025.3556936
ISSN
2169-3536
2169-3536
Abstract
Valve-side single-phase-to-ground (SPG) faults are atypical yet critical for the operation of half-bridge (HB) Modular Multilevel converter (MMC) bipolar or asymmetrical monopolar systems. For the impacted converter station, these faults may result in non-zero crossing currents on the connected AC grid and cause significant overvoltage on upper arm submodule (SM) capacitors. This article presents an SPG valve-side fault mitigation strategy using a power electronic (PE) fault current limiter (FCL) installed at the grounded terminal of the MMC converter, along with a mechanical DC breaker on the DC transmission line. The FCL transfers converter ground current to a resistive branch during the SPG fault, resulting in zero crossing currents on the AC side of the grid, thus ensuring fault current clearance by grid-side AC circuit breakers. Moreover, the proposed topology limits the fault current magnitude, reducing the impact of SPG valve-side faults on the AC grid. The discontinuous DC line current is cleared by a fast mechanical DC circuit breaker, halting the charging of the upper arm SM capacitor and limiting the overvoltage stress on converter insulation. In addition, the severity of upper arm SM overvoltage in case of SPG fault in long distance HB-MMC bipolar links has been assessed, and the prospect of a passive oscillation DC circuit breaker to curb such overvoltage has been demonstrated. The effectiveness of the protection topology has been verified through PSCAD/EMTDC software and compared with previously proposed SPG fault clearance methods. © 2013 IEEE.
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ERICA 공학대학 (SCHOOL OF ELECTRICAL ENGINEERING)
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