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Design Methodology for Low-Voltage Operational (≤1 V) FRAM Cell Capacitors and Approaches for Overcoming Disturb Issues in 1T-nC Arrays: Experimental & Modeling Go to Link

Lee, Sangho; Kim, Giuk; Kim, Chaeheon; Jung, Yangjin; Hwang, Jeonghyun; Nam, Yunseok; Shin, Mincheol; Goh, Youngin; Ryu, Mintae; Suh, Jihye, et al.

ArticleIssue Date2025CitationTechnical Digest - International Electron Devices Meeting, pp 1 - 4

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Engineering Negative Capacitance in Hf0.5Zr0.5O2 for Low-Power and Reliable Charge Trap Flash Memory Go to Link

Nam, Yunseok; Lee, Sangho; Jung, Yangjin; Kim, Kang; Ok, Jihye; Ha, Jinwook; Yoon, Heemin; Shin, Mincheol; Park, Sang-Hee Ko; Ahn, Jinho, et al.

ArticleIssue Date2026CitationACS APPLIED MATERIALS & INTERFACES, v.18, no.1, pp 3065 - 3073PublisherAMER CHEMICAL SOC

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Enhancement of performance and reliability in MOSFETs via high-pressure microwave annealing Go to Link

Kang, Geonhyeong; Shin, Hunbeom; Kim, Seungyeob; Zhang, Lingwei; Kim, Giuk; Lee, Sujeong; Nam, Yunseok; Kim, Chaeheon; Kim, Hoon; Ahn, Jinho, et al.

ArticleIssue Date2025CitationJournal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures, v.43, no.1, pp 1 - 6PublisherAmerican Institute of Physics

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Experimental Analysis on the Interaction Between Interface Trap Charges and Polarization on the Memory Window of Metal-Ferroelectric-Insulator-Si (MFIS) FeFET Go to Link

Kim, Giuk; Choi, Hyojun; Lee, Sangho; Shin, Hunbeom; Lee, Sangmok; Nam, Yunseok; Kang, Hyunjun; Shin, Seokjoong; Kim, Hoon; Lim, Youngjin, et al.

ArticleIssue Date2024CitationIEEE TRANSACTIONS ON ELECTRON DEVICES, v.71, no.11, pp 6627 - 6632PublisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

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Imprinted Antiferroelectric with Low Damage Process for High Performance Negative Capacitance NAND Flash Memory Go to Link

Lee, Sangho; Kim, Giuk; Nam, Yunseok; Jeong, Yeongseok; Kim, Taeho; Shin, Hunbeom; Lee, Sangmok; Ahn, Jinho; Jeon, Sanghun

ArticleIssue Date2025CitationIEEE Electron Device Letters, v.46, no.4, pp 572 - 575PublisherInstitute of Electrical and Electronics Engineers

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In-depth Analysis of the Hafnia Ferroelectrics as a Key Enabler for Low Voltage & QLC 3D VNAND beyond 1K Layers: Experimental Demonstration and Modeling Go to Link

Kim, Giuk; Choi, Hyojun; Shin, Hunbeom; Lee, Sangho; Lee, Sangmok; Nam, Yunseok; Jung, Minhyun; Myeong, Ilho; Kim, Kijoon; Woo, Jongho, et al.

ArticleIssue Date2024CitationDigest of Technical Papers - Symposium on VLSI Technology, pp 1 - 2

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Stabilization of Morphotropic Phase Boundary in Hafnia via Microwave Low-Temperature Crystallization Process for Next-Generation Dynamic Random Access Memory Technology Go to Link

Shin, Hunbeom; Kim, Giuk; Lee, Sujeong; Choi, Hyojun; Lee, Sangho; Lee, Sangmok; Nam, Yunseok; Kang, Geonhyeong; Kim, Hyungjun; Ahn, Jinho, et al.

ArticleIssue Date2024Citationphysica status solidi (RRL) - Rapid Research Letters, v.18, no.9, pp 1 - 7PublisherWiley - VCH Verlag GmbH & CO. KGaA

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Stabilized negative capacitance for near-theoretical efficiency and high reliability in charge trap flash memory Go to Link

Lee, Sangho; Kim, Giuk; Nam, Yunseok; Jeong, Yangjin; Kang, Hyunjun; Kim, Woongjin; Shin, Hunbeom; Shin, Mincheol; Park, Sanghyun; Seo, Kwangyou, et al.

ArticleIssue Date2025CitationMaterials Today Physics, v.58, pp 1 - 10PublisherELSEVIER SCIENCE BV

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The Opportunity of Anti-ferroelectrics in FeFET for Emerging Non-Volatile Memory Applications Go to Link

Choi, Hyojun; Kim, Giuk; Shin, Hunbeom; Nam, Yunseok; Jeon, Sanghun; Kim, Kwangsoo; Lim, Suhwan; Woo, Jongho; Kim, Wanki; Ha, Daewon, et al.

ArticleIssue Date2025CitationIEEE International Reliability Physics Symposium Proceedings, pp 1 - 6

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Browsing by Nam, YunseokAuthor

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