A Real-Time, 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFETopen access
- Authors
- Wang, Angie; Bae, Woorham; Han, Jae duk; Bailey, Stevo; Ocal, Orhan; Rigge, Paul; Wang, Zhongkai; Ramchandran, Kannan; Alon, Elad; Nikolic, Borivoje
- Issue Date
- Jul-2019
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Analog-to-digital converters (ADCs); Berkeley Analog Generator (BAG); Constructing Hardware in a Scala Embedded Language (Chisel); fast Fourier transform (FFT); hardware generators; fifth-generation reduced instruction set computer (RISC-V); spectrum sensing
- Citation
- IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.54, no.7, pp.1993 - 2008
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE JOURNAL OF SOLID-STATE CIRCUITS
- Volume
- 54
- Number
- 7
- Start Page
- 1993
- End Page
- 2008
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/147410
- DOI
- 10.1109/JSSC.2019.2913099
- ISSN
- 0018-9200
- Abstract
- A 1.89-GHz bandwidth, 175-kHz resolution spectral analysis system-on-chip (SoC), integrating a subsampling analog-to-digital converter (ADC) frontend with a digital reconstruction backend and implementing a 21 600-point sparse Fourier transform based on the fast Fourier aliasing-based sparse transform (FFAST) algorithm has been co-designed by using the Constructing Hardware in a Scala Embedded Language (Chisel) and Berkeley Analog Generator (BAG) circuit generator frameworks in 16-nm CMOS. Three sets of 25x, 27x, and 32x sub-sampling successive approximation register (SAR) ADCs acquire signal with similar to 5.4-6.3 effective number of bits (ENOB)/slice. The digital backend consists of mixed-radix 864-, 800-, and 675-point fast Fourier transforms (FFTs), a signal location estimator, and a peeling decoder that recovers aliased signals from a sparsely populated spectrum. A single-issue, in-order, fifth-generation reduced instruction set (RISC-V) Rocket processor interacts with the spectrum analyzer for post-processing and calibration. The ADC consumes 49.8 mW with a 3.78-GHz reference clock. At 400 MHz and 0.7-V digital supply voltage (VDD), the Rocket core and the FFAST digital signal processing (DSP) together consume 133.5 mW.
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