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SCIESCOPUS
100-112-Gb/s 1.6-Vppd PAM-8 Transmitters With High-Swing 3+1 Hybrid FFE Taps in 40-nm TechnologyGo to Link

Song, Eunji; Yang, Jeonghyu; Oh, Youngmin; Hong, Seungwook; Lee, Dongjun; Lee, Sangwan; Im, Hyunwoo; Shin, Taeho; Han, Jaeduk

ArticleIssue Date2025CitationIEEE Journal of Solid-State Circuits, v.60, no.2, pp 543 - 554PublisherInstitute of Electrical and Electronics Engineers
SCOPUS
6.8 A 100Gb/s 1.6VppdPAM-8 Transmitter with High-Swing 3+1 Hybrid FFE Taps in 40nmGo to Link

Yang, Jeonghyu; Song, Eunji; Hong, Seungwook; Lee, Dongjun; Lee, Sangwan; Im, Hyunwoo; Shin, Taeho; Han, Jaeduk

ArticleIssue Date2023CitationDigest of Technical Papers - IEEE International Solid-State Circuits Conference, v.2023-February, pp 122 - 124PublisherIEEE
SCIESCOPUS
A 100-Gb/s PAM-8 Transmitter With 3-Tap FFE and High-Swing Hybrid Driver in 40-nm CMOS TechnologyGo to Link

Oh, Youngmin; Im, Hyunwoo; Yang, Jeonghyu; Song, Eunji; Lee, Dongjun; Lee, Sangwan; Shin, Taeho; Han, Jaeduk

ArticleIssue Date2024CitationIEEE Transactions on Circuits and Systems II: Express Briefs, v.71, no.6, pp 2936 - 2940PublisherInstitute of Electrical and Electronics Engineers
SCIESCOPUS
A 36-Gb/s Single-Ended PAM-4 Receiver With Voltage-Feedback DFE in 40-nm CMOS TechnologyGo to Link

Sim, Taeyang; You, Geunyoung; Jung, Hwanseok; Lee, Donghun; Shin, Taeho; Han, Jaeduk

ArticleIssue Date2026CitationIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.73, no.4, pp 2759 - 2770PublisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
SCOPUS
A 56-Gb/s 0.39-pJ/bit PAM-4 Transmitter Frontend with Shunt-Ffe Tail-Less Driver and External Bias-TeesGo to Link

Jang, Yooseong; Yun, Seokmin; Yang, Jeonghyu; Shin, Taeho; Song, Eunji; Han, Jaeduk

ArticleIssue Date2025CitationIEEE International Symposium on Circuits and Systems proceedings, pp 1 - 5
SCIESCOPUS
A Driver-Current-Regulated 120-Gb/s PAM-8 7-bit DAC-Based Transmitter in 28-nm CMOSGo to Link

Shin, Taeho; Jang, Yooseong; Yun, Seokmin; Yang, Jeonghyu; Han, Jaeduk

ArticleIssue Date2025CitationIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.72, no.12, pp 1977 - 1981PublisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
SCOPUS
A SCAN Chain Generator for Verification of Full-Custom Integrated CircuitsGo to Link

Shin, Taeho; Han, Jae duk

ArticleIssue Date2021CitationProceedings - International SoC Design Conference 2021, ISOCC 2021, pp.335 - 336PublisherIEEE
SCIESCOPUS
LAYGO2: A Custom Layout Generation Engine Based on Dynamic Templates and Grids for Advanced CMOS TechnologiesGo to Link

Shin, Taeho; Lee, Dongjun; Kim, Dongwhee; Sung, Gaeryun; Shin, Wookjin; Jo, Yunseong; Park, Hyungjoo; Han, Jaeduk

ArticleIssue Date2023CitationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v.42, no.12, pp 4402 - 4412PublisherInstitute of Electrical and Electronics Engineers
SCOPUS
Process-Portable Layout Generation of High-Speed Digital Circuit Using Standard Cells in FinFETGo to Link

Kang, Taeseung; Shin, Taeho; Kim, Heejun; Han, Jaeduk

ArticleIssue Date2025Citation2025 21st International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuits Design (SMACD), pp 1 - 4PublisherInstitute of Electrical and Electronics Engineers Inc.
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